Driving factors in modern, high-voltage DC-DC power conversion include size and efficiency. While the maturation of resonant converter circuits and supporting component technologies has decreased the volume of the converters' front-end, the process of inverting high-frequency, high-voltage on the output has not changed significantly over several decades. Designers continue to weigh the trade-off between diode recovery time and reverse breakdown voltage required by silicon devices as discussed further in J. Wang, et al., “Characterization, Modeling of 10-kV SiC JBS Diodes and Their Application Prospect,” IEEE Energy Conversion Congress and Exposition (ECCE), pp. 1488-1493 (2009). From a system perspective, one can use high-speed, lower-voltage diodes and a transformer with many secondary windings; lower-speed, high-voltage diodes with fewer secondary windings; or series-connected multiple, high-speed, lower-voltage diodes using a reduced number of secondary windings. In all of these approaches, the output rectifier impacts system size and performance.
Researchers are pushing the bounds of conventional packaging methods and materials to address the needs of high voltage (HV) components. Motto and Yamamoto in “New High Power Semiconductors: High Voltage IGBTs and GCTs” PCIM'98 Power Electronics Conference Proceedings, pp. 296-302, (1998), reported on the development of a 6 kV insulated-gate bipolar transistor module in which the direct bonded copper (DBC) metallization patterns had rounded corners and increased edge margins to reduce electric field intensities. Also, low-pressure processing was used to minimize void creation and decrease associated partial discharge (PD) degradation. PD is usually initiated in gas-filled voids within the dielectric system. Because the dielectric constant of the gas is much less than that of the solid dielectric, the electric field within the void reaches the corona inception voltage of the gas before the solid. The plasma generated within the void, in turn, degrades the surrounding dielectric through chemical and physical attack and ultimately leads to the failure of the dielectric system as described in P. H. F. Morshuis, “Degradation of Solid Dielectrics Due to Internal Partial Discharge: Some thoughts on progress made and where to go now”, IEEE Trans. Dielectr. Electr. Insul., Vol. 12, pp. 905-913, (2005).
Partial discharge free, 0.63-mm DBC substrates at electric fields of up to 12 MV/m were reported in Schulz-Harder and K. Exel, “Advanced DBC Substrates for High Power and High Voltage Electronics,” Proceeding of 22nd IEEE SEMI-THERM Symposium, Dallas, Tex., Mar. 14-16, 2006, pp. 230-231. With the maturation of wide band-gap semiconductor materials, however, single die can now achieve breakdown voltages in excess of 10 kV, as reported in R. J. Callanan, et al., “Recent Progress in SiC DMOSFETs and JBS Diodes at CREE,” Proceedings of 34th IEEE Industrial Electronics Conf., Orlando, Fla., Nov. 10-13, 2008, pp. 2885-2890. These components require new methods and materials to realize their full benefit.
The development of high-voltage (HV) components has been accelerated with recent advances in the material quality of the semiconductor silicon carbide (SiC) as described in J. Wang, et al., “Characterization, Modeling of 10 kV SiC JBS Diodes and Their Application Prospect,” IEEE Energy Conversion Congress and Exposition, 2009; pp. 1488-1493, 20-24 September 2009 and B. A. Hull, et al., “Performance and Stability of Large-Area 4H—SiC 10-kV Junction Barrier Schottky Rectifiers,” IEEE Trans. Electron Devices, vol. 55, pp. 1864-1870, August 2008. However, there have been relatively few reports of packaging advances that support the use of components operating above 6 kV.
A schematic of a full bridge rectifier (FBR) circuit 10 is shown in FIG. 1, including terminals 14. In the FBR, four diodes are interconnected, as shown in FIG. 1, to transform (rectify) the bipolar electrical signal applied to the AC terminals (14AC) to a unipolar signal at the positive (+) and negative (−) terminals 14. FIG. 2 illustrates the conventional approach to packaging a high voltage (HV) full bridge rectifier (FBR) 10A. The case is constructed from a high-temperature plastic with four terminals 14. The diode die are connected to the terminals and positioned within the plastic case. The case is then filled with an epoxy- or silicone-based encapsulant, which provides mechanical support. The module is designed so that the packaging materials electrically isolate the internal diode structure from its surroundings. To ensure reliable operation, the manufacturer specifies the maximum voltage isolation between the module and mounting surface, which is opposite the terminals. In this packaging approach, however, there is high thermal resistance between the diodes and external heat-conducting bodies. Heat generated within the diodes is not effectively transmitted out of the package. For this reason, the current rating of the FBR must be significantly de-rated, with respect to the capability of the diodes, to avoid failure. Typically, operational current de-rating begins at case temperatures of approximately 55° C. and can be reduced by 100% at 175° C., as described in “KBPC35005 Thru KBPC3510 datasheet,” Shanghai Chenyi Electronics Co. Ltd., (2000).
There are several finite element analysis tools that are used to solve three-dimensional heat transfer problems. The baseline thermal performance of the conventional full bridge rectifier (FBR) was obtained using the computational fluid dynamics program SolidWorks® Flow Simulation by Dassault Systemes Solid Works Corp., and accepted material properties and power loss estimates. FIG. 3A illustrates the simulation model of the conventional FBR with four diodes 15 suspended within the encapsulation and mounted on a copper plate. Each diode dissipates 8 W and the ambient temperature is 20° C. FIG. 3B shows the steady-state thermal profile where the diode and baseplate temperatures reach approximately 209° C. and 69° C., respectively. As noted previously, silicon diodes are operated below 175° C. (and more often below 125° C.) because of high-temperature performance degradation. A diode temperature of 209° C. is clearly not acceptable, and a packaging scheme with lower thermal resistance is needed to better utilize the semiconductor devices in this scheme. In the following sections, these results will be compared with another commercial approach and the embodiments of the present invention.
In addition to the thermal aspects of packaging design, deterioration of the packaging materials due to electric field stress must also be considered. Partial or corona discharge within electrical insulation systems is a deteriorating mechanism in HV packaging as reference in P. H. F. Morshuis, “Degradation of Solid Dielectrics Due to Internal Partial Discharge: Some thoughts on progress made and where to go now,” IEEE Trans. Dielectr. Electr. Insul., vol. 12, pp. 905-913, October 2005. The dielectric strengths of the materials determine the maximum electric field that can be supported before these materials become conductive (dielectric breakdown). In practice, however, the maximum useable dielectric strength is much less than theoretical values. Partial discharge (PD) is usually initiated in gas-filled voids within the dielectric system. Because the dielectric constant of the gas is much less than that of the solid dielectric, the electric field within the void reaches the corona inception voltage of the gas before the solid. The plasma generated within the void, in turn, degrades the surrounding dielectric and ultimately leads to failure of the electrical isolation system. To ameliorate partial discharge (PD) degradation, electric fields should be minimized by increasing the spacing between HV conductors and by eliminating sharp edges or points on conductors that act as electric field concentrators.
In U.S. Pat. No. 4,563,383 to Kuneman and Dickson entitled “Direct Bond Copper Ceramic Substrate for Electronic Applications,” discloses a multilayered direct-bond copper (DBC) substrates for electronics packaging. Widely used in modem electronics, the typical embodiment consists of a sheet ceramic, usually aluminum nitride (AIN) or aluminum oxide, clad on both sides by a thin layer of copper. The DBC structure allows for higher-density packaging through improved heat transfer and electrical isolation of components mounted to the copper layers.
A top view of a planar DBC-based full bridge FBR 20 is shown in FIG. 4. As used herein, the terminology “planar” refers to die mounted on a ridged, metalized substrate. In this figure, the lighter regions represent ceramic 21, the gray regions represent the diode die 22, and the intermediate regions are top metal pads 23 operatively connected to terminals 24. Note that the diode die 22 are also multilayered structures in that their top and bottom surfaces are the anodes and cathodes, respectively. The DBC substrate is patterned with four pads for the diode die and terminals. One pad is large enough to provide the electrical interconnection of two diodes (cathodes), whereas bond wires are used to make all other connections. The overlaid electrical schematic shows the diode interconnections, some of which have not been included in the simulation model.
FIG. 5 shows a simplified cross-sectional view of the FBR 20 illustrated in FIG. 4 taken along the line A-A′. Each semiconductor die 22 (comprising an anode 26 made of Al and a silicon (or silicon carbide) layer 31, is mechanically and electrically connected to the substrate by a thin layer of solder 28 as shown in FIG. 5. Layer 23 is generally formed of copper. Since the copper layers may be patterned, an entire circuit consisting of passive components, such as resistors and capacitors, as well as semiconductor devices may be constructed, Similarly, the substrate 29 is attached to the baseplate 27 by a solder layer 25. The ceramic layer 21 (which may be for example aluminum nitride (AIN) or aluminum oxide) provides electrical isolation between the circuit and the baseplate 27. In a typical application, such as a 1200 V insulated gate bipolar transistor module, the die 22 are soldered to the top DBC layer and a baseplate 27 is soldered (by solder 25) to the bottom DBC layer 32 (Cu) as illustrated in FIG. Assuming a baseplate isolation voltage of approximately 2500 V, and using readily available materials, this structure is relatively robust from an electrical reliability perspective and has relatively good thermal performance.
Relative to the conventional high voltage (HV) FBR of FIGS. 2, 3A and 3B previously described, the planar structure provides a lower thermal resistance path from the semiconductor die to the baseplate. This enables the components to be operated at higher baseplate temperatures or higher power dissipations without the penalty of significant electrical performance derating. FIG. 6 shows the simulated die temperature of a planer DBC structure using the same material and loss parameters of the conventional package simulation. Here, the maximum die temperature of the planar package is approximately 67° C. or three times lower than that of the conventional package. Note that there is only a 3° C. temperature difference between the diode and baseplate. This is believed to be due to the higher thermal conductivity of ceramics (approximately 180 W/m·K for AlN) versus that of the organic encapsulants (approximately 1 W/m·K) and the shorter distance between the diode and ambient.
Since the ceramic layer also provides electrical isolation of the circuit from the baseplate, it must be thick enough to withstand the applied voltages. Bulk AIN has a typical breakdown voltage range of 12-17 MV/m. Therefore, to provide the commercial and industrial isolation voltage of approximately 2.5 kV, a 210 μm layer of AlN is required. It is recognized, however, that one of the impediments of using direct bonded copper (DBC) in high voltage (HV) packaging is the onset of PD at approximately 60% of the dielectric strength of the bulk ceramic. This behavior is attributed to voids between the copper and ceramic, irregularities on the etched copper/ceramic interface, and solder residues. For a further description, see G. Mitic and G. Lefranc, “Localization of Electrical-Insulation and Partial-Discharge Failures of IGBT Modules,” IEEE Trans. Ind. Appl, vol. 38, no. 1, pp. 175-180 (2002) and Schulz-Harder and K. Exel, “Advanced DBC Substrates for High Power and High Voltage Electronics,” Proceeding of 22nd IEEE SEMI-THERM Symposium, Dallas, Tex., Mar. 14-16, 2006, pp. 230-231. For example, PD in AlN DBC has been reported at fields of 7 MV/m. Because of manufacturing issues (mechanical stress), 254 μm is usually the minimum AIN thickness commonly used in packaging, while 500 μm is the maximum thickness. At 500 μm, the voltage difference between the semiconductor die and baseplate should not exceed approximately 3.5 kV in order to avoid long-term failure modes.
It is noted that in U.S. Patent Application Publication 20070257343 to M. Hauenstein, et al., entitled “Die-on-Leadframe (DOL) with High Voltage Isolation,” there is proposed an alternative packaging approach to improve thermal performance and provide dielectric isolation by employing a thin curable insulation layer to replace the ceramic substrate. Although the thin organic layer provides lower mechanical stress, it cannot support high voltage (HV) isolation. Furthermore, the long-term reliability issue of partial discharge (PD) within the insulation layer was not addressed. Likewise, in U.S. Pat. No. 6,991,961 to R. L. Hubbard, et al, entitled “Method of Forming a High-Voltage/High-Power Die Package,” there is proposed a flexible packaging scheme for power components operating at <2 kV but without consideration of thermal or reliability issues.